library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity CONV_STD_DIR is
    port(
         clk: in std_logic;
         Xstd: in std_logic;
	 		Ystd: in std_logic_vector(14 downto 0);
	 		Zstd: in std_logic_vector(14 downto 0);
	 		Ydir: out std_logic_vector(8 downto 0);
	 		Zdir: out std_logic_vector(8 downto 0)
   	);
end CONV_STD_DIR;

-- Esto lo unico que hace es esta cuenta (si X>0):
--160+160*Y
--160-160*Z

--160*Y=Y&"0000"/1000=(Y&"0000")*131/131072


architecture Convertir of CONV_STD_DIR is
begin
   process(clk)
       --constant N131: std_logic_vector(7 downto 0):="10000011";
       variable M: std_logic_vector(17 downto 0);
       variable prod: std_logic_vector(24 downto 0);
   begin
       if rising_edge(clk) then
           if Xstd='0' then
					M:=Ystd(13 downto 0)&"0000";
               if Ystd(14)='1' then
                  M:=(not(M)+1);
               end if;
               prod:=("0000000"&M)+("000000"&M&'0')+(M&"0000000");--prod:=M*N131;
               if Ystd(14)='0' then
                  Ydir <= "010100000" + prod(24 downto 16);
               else 
                  Ydir <= "010100000" - prod(24 downto 16);
               end if;
               M:=Zstd(13 downto 0)&"0000";
               if Zstd(14)='1' then
                  M:=(not(M)+1);
               end if;
               prod:=("0000000"&M)+("000000"&M&'0')+(M&"0000000");--prod:=M*N131;
               if Zstd(14)='0' then
                  Zdir <= "010100000" - prod(24 downto 16);
               else 
                  Ydir <= "010100000" + prod(24 downto 16);
               end if;
           end if;
       end if;
   end process;
end Convertir; 
